Organic Light-Emitting Diodes (OLEDs) have outstanding features such as self-luminosity, a high contrast, a small thickness, a wide viewing angle, fast responsivity, applicability to a flexible display panel, a wide range of operation temperatures, and a simple construction and manufacturing process, need not for a backlight, and hence have been regarded as emerging technology for the next generation of flat panel displays.
In the related art, power lines of an OLED display are typically disposed in a pixel region, driving elements and driven elements are connected between the power lines, and an image is displayed as desired by controlling conductance of the driving elements. If a thin-film transistor is employed as the driving element, a source electrode of the thin-film transistor is connected to a power supply, and a voltage corresponding to displayed data is applied to a gate electrode of the thin-film transistor, so that electric current corresponding to a voltage across the gate electrode and the source electrode of the thin-film transistor is supplied to the driven element. Wiring interconnections between different thin-film transistors are required for circuitry in the pixel region of the OLED display, and are realized by means of via holes in an insulating layer.
At present, the via hole is formed by directly etching a gate insulation layer to expose a gate electrode metal, then a source-drain electrode metal covers the via hole and connects the gate electrode metal. In the design of the via hole, the periphery of the source-drain electrode metal need extend beyond an edge of the via hole by a sufficient distance, to ensure that the source-drain electrode metal completely covers the via hole, thereby preventing the exposure of the gate electrode metal. Otherwise, in etching the source-drain electrode metal, there is a risk that the gate electrode metal is etched and hence the resistance of a connection based on the via hole is too large and the via hole is eroded. If an area of the source-drain electrode metal is large enough, the risk of etching the gate electrode metal around the via hole by mistake is reduced, whereas the area of the source-drain electrode metal around the via hole is too large. Considering exposure precision, wirings for the source-drain metal around the via hole need to be far away from the via hole, causing difficulties in designing an OLED pixel circuit, which is disadvantageous for improving Pixels Per Inch (PPI) and stability of the OLED display.